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How can we take the hand on ESP32 core with JTAG and stop the cores correctly without having tons of reset.I think the main issue is probably watchdog on ESP32 which is not refreshed anymore (because JTAG take the hand and do not stop the watchdog too early. Rst:0x1 (POWERON_RESET),boot:0x3 (DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2)) Like you can see the ESP32 crash often and reboot I can see it clearly in the Terminal with output: Info : esp32.cpu0: Core was reset (pwrstat=0x3F, after clear 0x00). In procedure 'esp32.cpu0' called at file "/usr/local/share/openocd/scripts/target/esp32.cfg", line 37Įrror: esp32.cpu0: xtensa_write_memory (line 1024): DSR (00010007) indicates target still busy!Įrror: esp32.cpu0: xtensa_write_memory (line 1024): DSR (00010007) indicates DIR instruction generated an exception!
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Warn : esp32.cpu0: Failed writing 4 bytes at address 0x3FF5F064 Info : esp32.cpu0: Debug controller was reset (pwrstat=0x40, after clear 0圆0).Įrror: esp32.cpu0: esp108_fetch_all_regs (line 649): DSR (00730007) indicates target still busy!Įrror: esp32.cpu0: esp108_fetch_all_regs (line 649): DSR (00730007) indicates DIR instruction generated an exception!Įrror: esp32.cpu0: esp108_fetch_all_regs (line 673): DSR (00730007) indicates target still busy!Įrror: esp32.cpu0: esp108_fetch_all_regs (line 673): DSR (00730007) indicates DIR instruction generated an exception!Įrror: esp32.cpu0: xtensa_write_memory (line 1024): DSR (00010002) indicates DIR instruction generated an exception! Info : esp32.cpu0: Core was reset (pwrstat=0x3F, after clear 0x40). Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F). Info : esp32.cpu0: Core was reset (pwrstat=0x5F, after clear 0x0F). Info : esp32.cpu0: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).